NTA UGC NET/JRF Exam, December-2023 (Electronic Science)

Total Questions: 100

11. The value of the unknown node voltage Vₜ in the following circuit is:

Correct Answer: B. V₁ = 1.071 V
Solution:

To find the unknown node voltage V₁ in the given circuit, we can use Kirchhoff's Current Law (KCL) at node V₁. According to KCL, the sum of currents entering a node is equal to the sum of currents leaving the
node.
Identify the currents at node V₁:
• There is a current source of -8A entering the node.
• There is a current of 3A leaving the node.
There is a current through the 4Ω resistor from V₁ to the 22V source.
• There is a current through the 3Ω resistor
from V₁ to the reference node (OV).
Set up the KCL equation at node V₁:

Simplify the equation:
Multiply through by 12 (the last common multiple of 4 and 3) to clear the fractions:Hence, the calculated voltage at node V₁ is approximately 1.071V.

12. Which of the following represents an ideal current source(es) and ideal voltage source(es) behaviour?

Correct Answer: B.
Solution:Ideal Current Source (CS): An ideal current source provides a constant current regardless of the voltage across it. The characteristic graph of an ideal current source is a vertical line at the value of the current it provides, indicating that the current remains constant even as the voltage varies.

Ideal Voltage Source (VS): An ideal voltage source provides a constant voltage regardless of the current flowing through it. The characteristic graph of an ideal voltage source is a horizontal line at the value of the voltage it provides, indicating that the voltage remains constant even as the current varies.
Let's examine the options:
• Option A: The graph shows a non-constant behaviour for both current and voltage sources, which is incorrect.
• Option B: The graph shows a vertical line for the current source and a horizontal line for the voltage source. This correctly represents the ideal behaviour of an ideal current source and an ideal voltage source.
• Option C: The graphs do not represent the ideal behaviours, showing oscillatory patterns that are incorrect.
• Option D: The graphs do not match the ideal behaviours of the sources, showing incorrect representations.

Therefore, the correct answer is B, as it accurately depicts the ideal current source with a vertical line and the ideal voltage source with a horizontal line.

13. The output voltage (Vₒ) of the converter (IC 9400) is related to the input frequency (Fim) by the equation:

Correct Answer: A.
Solution:The output voltage V, of the converter (IC 9400) is related to the input frequency Fin by the given equation:
The correct equation, provided in option A, indicates that the output voltage is directly proportional to the input frequency. As the input frequency increases, the output voltage increases linearly, assuming that the reference voltage, capacitance, and internal resistance are constants.

14. For an inverting comparator circuit acting as a Schmitt Trigger, as shown in figure below, the expression of Hysteresis Voltage (Vₙᵧ) is given by:

Correct Answer: D.
Solution:For an inverting comparator circuit acting as a Schmitt Trigger, the hysteresis voltage Vₕᵧ is given by:This equation can be derived by analyzing the feedback network of the Schmitt Trigger, where R₁ and R₂ form a voltage divider. The ouput voltage Vₒ can swing between +Vₛₐₜ and -Vₛₐₜ. The hysteresis voltage is the difference in the input voltage required to switch the output from one saturation level to the other.

The voltage at the inverting input of the opamp (reference voltage) changes according to the output voltage and is given by the voltage divider formed by R₁ and R₂:When the output switches between +Vₛₐₜ and -Vₛₐₜ, the difference in reference voltage across the hysteresis range is:Hence, the expression for the hysteresis voltage is correctly represented by option D.

15. For a FET based phase shift oscillator, what should be the value of capacitor (C) for oscillator operation at 1 kHz. The resistor (R) in the feedback network is 20 kΩ.

Correct Answer: D. 3.25 × 10⁻⁹ F
Solution:

For a FET-based phase shift oscillator operating at a frequency f = 1 kHz, we need to find the value of the capacitor C in the feedback network. The resistor R in the feedback network is given as 20 k. The frequency of oscillation for a phase shift oscillator is given by:Thus, the value of the capacitor C for the oscillator operation at 1 kHz is 3.25 × 10⁻⁹ F.

16. Calculate the current I through each of the transistor Q₂ and Q₃ in the circuit given below:

Correct Answer: B. 5.3 mA
Solution:

To calculate the current I through each of the transistors Q₂ and Q₃ in the given circuit, we start by analyzing the control current I𝔠ₒₙₜᵣₒₗ through the resistor connected control to Q₁.
Determine I𝔠ₒₙₜᵣₒₗ: The voltage across the base-emitter junctions of the transistors is given as VBE = 0.7V. The voltage drop across the resistor R = 1 ΚΩ can be calculated by subtracting the base-emitter voltage from the supply voltageSince the circuit indicates that I through Q₂ and Q₃ is the same as I𝔠ₒₙₜᵣₒₗ, each transistor Q₂ and Q₃ will have the current I equal to I𝔠ₒₙₜᵣₒₗ.

Therefore, the current I through each of the transistors Q₂ and Q₃ is 5.3 mA.

17. If (1235)ₓ = (3033)ᵧ, where x and y indicate the bases of the corresponding numbers, then:

Correct Answer: C. x = 8 and y = 6
Solution:

To determine the bases x and y for the numbers (1235)ₓ and (3033)ᵧ such that they are equal, we need to convert both numbers to a common base, typically base 10 and equate them.We test each option to find the correct pair of bases:Thus, the correct answer is C: x = 8 and y = 6.

18. In a J-K FF, if J = Q and K = 1 (see figure). Assuming the flip flop was initially cleared and then clocked for 6 pulses, the sequence at the Q output will be:

Correct Answer: D. 010101
Solution:

To determine the sequence at the Q output for the J-K flip flop with the given conditions, we need to follow the behaviour of the J-K flip flop and analyze it through each clock pulse. Given the conditions J = Q and K = 1:
1. Initial State:
• Assume the flip flop is initially cleared, meaning Q = 0.
2. Behaviour of the J-K Flip Flop:
• When J = Q and K = 1, the J-K flip flop toggles its output.
This means that if Q = 0, then J = 1 and the flip flop will toggle to Q = 1.
• If Q = 1, then J = 0 and the flip flop will toggle to Q = 0.
Let's go through the sequence for 6 clock pulses:
1. Pulse 1:
Initial Q = 0, so J = 1.
• The flip flop toggles: Q = 1.
2. Pulse 2:
Current Q = 1, so J = 0.
• The flip flop toggles: Q = 0.
3. Pulse 3:
Current Q = 0, so J = 1.
• The flip flop toggles: Q = 1.
4. Pulse 4:
• Current Q = 1, so J = 0.
• The flip flop toggles: Q = 0 .
5. Pulse 5:
• Current Q = 0, so J = 1.
• The flip flop toggles: Q = 1.
6. Pulse 6:
• Current Q = 1, so J = 0.
• The flip flop toggles: Q = 0.
Thus, the sequence of Q for 6 pulses is:
Q = 010101
This sequence matches the option D.
Explanation for Incorrect Options:
• Option A (010000): Incorrect because it does not account for toggling behaviour after each pulse correctly.
• Option В (011001): Incorrect as it incorrectly represents the toggling
sequence.
Option C (010010): Incorrect as it fails to toggle the ouput after each pulse.
Therefore, the correct answer is D: 010101.

19. The Boolean function Y = AB + CD is to be realized using only 2-input NAND gates. The minimum number of gates required are:

Correct Answer: B. 3
Solution:

To realize the Bollean function Y = AB + CD using only 2-input NAND gates, we need to first understand the transformations required to convert basic AND, OR and NOT operations using NAND gates.Let's break down the steps to implement Y = AB + CD:Total number of NAND gates used: 2 (for A B + 2 (for C D) + 3 (for OR operation) = 7 gates.

However, a more efficient configuration can be found as follows:

  • Combine steps 1 and 2 using direct NAND outputs without requiring extra inverters: 2 gates for A B and 2 gates for C.D
  • Final OR operation using 1 additional gate combining results from the two AND outputs directly.

Therefore, the correct minimum number of 2-input NAND gates requires is: B. 3 gates.

20. The simplification in minimal sum of product (sop) of using K-map is:

Correct Answer: D. Y = A'C + B'D'
Solution:

To simplify the given Boolean function Y = F(A, B, C, D) using a Karnaugh map (K-map), we will map the given minterms and don't-care terms onto a 4-variable K-map and find the minimal Sum of Products (SOP).
Given: